1. Field of the Invention
This invention relates generally to lead frames used for electrical connection to a semiconductor die. More specifically, this invention relates to a hybrid lead frame having both leads for conventional lead-to-die wire bonding and leads for power and ground bussing that extend over a surface of the semiconductor die. In particular, the bussing leads are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing.
2. State of the Art
Dynamic Random Access Memory (DRAM) devices are the most widely used type of memory device. The amount of single-bit addressable memory locations within each DRAM is increasing along with the need for greater memory part densities. This demand for greater memory densities has created a global market and has resulted in memory part standards in which many memory parts are regarded as fungible items. Thus, many memory parts operate according to well known and universally adopted specifications such that one manufacturer""s memory part is plug-compatible with another manufacturer""s memory part.
In prior art packages, the power and ground pins are typically located along the longitudinal edges of the chip. Moreover, in prior art multiple metal layer DRAM designs, the power is brought to the interior of the die by on-chip metal interconnects connecting the peripheral power bonding pads to the on-chip power buses for distribution. This requires that the Vcc (power) the Vss (ground) buses have their metal interconnect paths go over or under one another on the die.
Accordingly, the parent application to this invention provides a solution to the need in the art to produce memory parts which can fit within the packaging requirements of previous generations of memory parts. This need for xe2x80x9cplug-compatible upgradesxe2x80x9d requires that memory density upgrades are easy to effect in existing computer systems and other systems which use memory, such as video systems. This requires that greater density memory parts be placed within the same size packages as previous generations of memory parts with the same signal and power pinout assignments.
As part of this need for plug compatible upgrades is the need to be able to use existing chip production equipment to manufacture such plug compatible upgrades. That is, because of this need to manufacture similarly configured devices, in addition to the large capital expenditure of purchasing new equipment for successive products and the long lead time for setting up and manufacturing products from such equipment, there is a further need in the art to either modify existing equipment or, better yet, to modify the substructure of the product to be adaptable to manufacture on existing equipment. There is still a further need in the art to more efficiently manufacture CMOS dynamic random access semiconductor memory parts which utilize space-saving techniques to fit the most memory cells within a fixed die size using a single deposition layer of highly conductive interconnect. This need also includes manufacturing such memory parts in a shorter production time using fewer process steps to produce more competitively priced memory parts.
The resulting solution, as presented in the parent application to this invention, provides a chip/lead frame configuration having a conventional lead finger arrangement with LOC bussing leads so that both the lead fingers and bussing leads can be wire bonded to bond pads on a semiconductor chip without having the wire bonds cross over any other lead. This chip/lead frame configuration can be produced on existing chip manufacturing equipment, resulting in a semiconductor device that is plug compatible in conventional computer equipment. Because of the unique lead frame configuration, however, developed to address the above-identified needs, at least one difficulty has been foreseen during manufacturing. That is, it is difficult to maintain the bussing leads of the present invention from bending, flexing, and/or otherwise moving during the manufacturing process.
The use of LOC-type bussing leads is known in the art to provide the chip with power and ground leads near the bonding pads of the chip. Typically, however, these LOC bussing leads are used in conjunction with a LOC lead frame. Examples of such LOC configurations with LOC bussing leads are shown in U.S. Pat. No. 4,862,245 to Pashby and U.S. Pat. No. 5,286,679 to Farnworth et al. assigned to the assignee of the present invention. As illustrated in U.S. Pat. No. 5,331,200 to Teo et al., it has also been recognized in the art to provide LOC bussing leads that include lead fingers for LOC bonding of the bussing leads to the chip without the use of wire bonds. Similarly, in U.S. Pat. No. 5,252,853 to Michii, the bus bars are bonded directly to the power and ground bond pads of the semiconductor chip.
Because of the relatively small size and the delicate nature of the individual lead fingers of high pin count lead frames, the need to stabilize the leads during the manufacturing process has been recognized in the art. For example, in U.S. Pat. No. 5,352,633, a plastic material is applied to the leads for retaining them in a common plane. In addition, as described in U.S. Pat. No. 5,140,404 to Fogal et al. and assigned to the assignee of the present invention, a nonconductive plastic or polyamide carrier material supporting a layer of thermoplastic is attached to the leads of a lead frame and provides support for a semiconductor die.
Applying a material, such as a tape, to the leads of a lead frame, as described in the art, to hold the leads in relative position to one another is not sufficient to keep the bus bars of the lead frame of the present invention from flexing, bending and/or moving relative to one another during the manufacturing process. Thus, it would be advantageous to provide a structure and method for securing the bus bars in position during the manufacturing process.
In a preferred embodiment of the parent application, a memory device having at least 16 megabytes (224 bits) is uniquely formed in which highly conductive interconnects (such as metal) are deposited in a single deposition step. The invention is described in reference to an exemplary embodiment of a 16 megabyte Dynamic Random Access Memory in which only a single deposition layer of highly conductive interconnects are deposited in a single deposition step. The resulting semiconductor die or chip can be manufactured with existing production equipment and fits within an existing industry-standard 300 mil Small Outline J-wing (SOJ), Thin, Small Outline Package (TSOP) or other industry standard packages with little or no speed loss over previous double metal deposition layered 16 megabyte DRAM physical architectures. This is accomplished using a die orientation that allows for a fast, single metal speed path, together with the novel use of a lead frame to remove a substantial portion of the power bussing from the single deposition layer metal, allowing for a smaller speed-optimized DRAM. The use of a single deposition layer metal design results in lower production costs and shorter production time for a wide variety of memory parts, including, but not limited to, DRAM, SRAM, VRAM, SAM, and the like.
According to the present invention, a structure and method for securing the bus bars of the hybrid lead frame disclosed in the parent application are provided. More specifically, this invention provides at least one tape segment or other similar structure comprised of a nonconductive plastic, or other similar material as known in the art, across the bussing leads of the hybrid lead frame. The tape segment is preferably positioned between at least two bus bars proximate the edge of the location where the semiconductor die is to be positioned.
The tape segments of the present invention help maintain the bussing leads in relative position during the manufacturing process and keep the bussing leads from flexing, bending and/or otherwise moving relative to each other and the plane defined by the top surface of the bussing leads.
The present invention solves the above-mentioned needs in the art and other needs which will be understood by those skilled in the art upon reading and understanding the present specification.